Field of the Invention
The present invention relates to field effect transistor (FET) circuits for converting input ECL transistor logic levels to FET logic levels. More particularly, the present invention relates to an FET interface circuit including an enhancement device which converts either a dual rail or a single rail ECL chip select signal to an FET voltage level and single rail ECL address and data-in signals to true and complement FET voltage levels for use in FET semiconductor memories.
It is also intended that the same FET circuit can be used as an interface between small signal levels and FET semiconductor logic or memory devices in a synchronous or an asynchronous system.
Transistor memories fabricated by MOS fabrication techniques experience delays in memory access due to the limitations of MOS technologies. Efforts have been successful in reducing delay inherent with this technology. A typical drive for FET memories is accomplished with transistor-transistor logic, TTL, which can swing from 0 to 5 volts. The large voltage swing results in large current swings di/dt on the leads driving the FET memory array.
As the operational speed of reading and writing FET memory arrays has increased, these current swings have produced an external limitation on the signals used to drive the memory chips, while the actual internal access time of the memory has decreased from more than 100 ns to less than 20 ns. Increasing the speed of the input signals in an attempt to keep up with increasing memory speed results in more noise from large di/dt current changes and lead inductance which reduces the overall reliability of the memory system.
Emitter coupled logic (ECL) operates at much higher switching rates than TTL. Emitter coupled logic provides a nominal excursion between logic levels of .+-.0.5 volts, and worse case conditions a total peak to peak voltage excursion of 0.6 volts, with the possibility of only 0.1 volts of signals above and below the reference level, far less than the required drive levels for FET circuits. The present invention is directed to coupling low level, fast switching ECL voltage levels to FET circuits.
One approach to the foregoing problem is described in Electronics, Sept. 9, 1985, at page 94. The article describes an ECL to CMOS interface which uses BIMOS, a mixture of CMOS and bipolar technology to manufacture a single memory chip. The multiple process steps of integrating bipolar and CMOS technologies is necessarily complex and expensive and thus undesirable.
Another example of a bipolar logic level to FET logic level interface circuit is described in IBM Technical Bulletin, Volume 19, No. 8, January 1977, pages 2953-2954. This circuit provides a clocked circuit for receiving input ECL or TTL logic levels. This circuit requires three timing signals to couple the logic signals on the input modes to higher voltages suitable for driving an FET array. No method for converting the timing signals from ECL levels to the required FET voltage levels is given.
An example of an ECL to CMOS interface circuit using only CMOS devices is described in the Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 53-56. This interface circuit uses an input stage to shift the ECL signal by an adjustable amount in order to drive a standard CMOS inverter. The amount of level shifting is supplied by a feed-back control circuit which compensates for variations in threshold and power supply shifts. A considerable number of devices are involved in this control circuit which must match the devices in the interface circuit and which may dissipate DC power. Since there will need to be several interface circuits for one control circuit, the interface circuit may be physically remote from the control circuit and across-chip device mis-matches could be substantial for typical CMOS processes. Similarly, on-chip power supply distribution may result in different supply values at the control circuit than at the interface circuit. Thus, interfacing the very small signals typical to high speed systems (on the order of 100 mV) could be a problem. In addition, since only a very small swing is available to drive the inverter and since no means for differential drive is supplied, the delay through the interface circuit is larger than would be expected with a differentially driven circuit. Attempts to mitigate the across-chip matching problem through use of larger than minimum channel lengths would further degrade performance.
In a copending patent application entitled ECL TO FET INTERFACE CIRCUIT FOR FIELD EFFECT TRANSISTOR ARRAYS, Ser. No. 06/789,884 filed Oct. 10, 1985 in the name of S. E. Schuster an interface circuit for coupling bipolar logic circuit output signals to an FET logic array is described. The interface receives chip select signals and their complement on a dual rail input line. A small signal amplifier comprising an FET amplifier having an input FET transistor connected through its source and gate to the dual rail input terminals, converts the chip enable signal to a high level clocking signal. An FET dynamic sense amplifier receives a bipolar logic level to be converted to an FET logic level, and receives a reference level from the bipolar transistor logic circuit. Upon clocking of the dynamic sense amplifier by the small signal multiplier, the true and complementary FET logic levels corresponding to the input bipolar logic levels are provided by the dynamic sense amplifier.
The small signal multiplier includes a depletion device and thus requires an additional implant. With minimum negative gate-to-source voltage the device should be at threshold, therefore a depletion implant is needed. Variations in the depletion threshold voltage of the depletion device are directly reflected in the minimum amplitude of the input ECL level that can be detected. Also, since the circuit includes a depletion device, its operation is limited to dual rail applications.
The present invention is distinct in that it provides a means for shifting the ECL input level by slightly more than an enhancement device threshold so that an additional implant is not required. In addition, the sensitivities to threshold voltage variations are almost completely eliminated. The present invention employs enhancement devices and therefore, may be used with memories and logic circuits with both dual rail and single rail operation.